The present invention relates generally to power supplies and more specifically to switched power supplies.
Efficient and ever smaller size switched power supplies are in high demand in almost all electronics devices in a wide range of applications. For example, smaller and more efficient power supplies are needed in telecommunication and embedded system applications, Power-over-Ethernet (POE) applications, microprocessors and chipsets requiring precise and robust voltage regulation, personal computers, cellular telephones, personal digital assistants (PDAs), etc.
Switched power supplies that are controlled by a current level (e.g., flowing through a resistor) are typically based on control loops and analog components. An analog signal has a continuously varying value, with infinite resolution in both time and magnitude. Analog circuits can introduce problems. For example, analog circuit characteristics can vary with manufacturing process, operating voltage and temperature, and so can be difficult to tune. Analog circuits also tend to get hot, as the power dissipated is proportional to the voltage across the active elements multiplied by the current through them. Analog circuitry can also be sensitive to noise. Because of an analog signal's infinite resolution, any perturbation or noise on an analog signal necessarily changes the current value.
Digital control of switching power supply becomes more and more attractive. Compared with analog circuits, digital control system offers a number of advantages, such as programmability, high flexibility, fewer components, and advanced control algorithms.
The problems and benefits of digital controlled power supplies are described in more detail in “A Practical Introduction to Digital Power Supply Control” by Laszlo Balogh (2005 Texas Instruments Inc.) and in “Digital Control of Switching Power Converters” by Y. Liu et al. (Proceedings of the 2005 IEEE Conference on Control Applications), both of which are incorporated herein by reference.
Basic digitally controlled power supplies are based on the digital pulse width modulator (DPWM) architecture. A digital clock signal sets the time base to convert a duty cycle digital control word into a waveform duty cycle. This results in a drawback of digital control—the resolution of the pulse width modulation (PWM) signal. Specifically, due to the nature of the digital signal, the duty cycle generated by a DPWM can only provide discrete numbers. Therefore, the output voltage is also a discrete value.
In particular, a higher resolution requires a higher clock frequency. For a given needed resolution, the clock frequency needs to be increased if the switching frequency is to be increased. There are advantages in increasing the switching frequency as it allows a power stage with significantly smaller geometrical dimensions and at a reduced cost.
Several solutions have been proposed to increase the effective resolution without necessarily increasing the digital clock in the case of a DPWM-based architecture. These include (1) fast clock counter comparator, (2) dither method, (3) tapped delay line and (4) ring oscillator.
FIG. 1A shows the structure of a fast clock counter-comparator circuit 100. In this integrated circuit (IC), the reference voltage and feedback output voltage are converted to equivalent pulse signals separately. In every sampling period, a digital proportional-integral-derivative (PID) controller 104 samples these two pulse signals. A system counter 108 is used to generate the fixed sampling period and saw-tooth switching waveform. By comparing the saw-tooth waveform and the numerical duty cycle value, the switch of converter 112 is turned on/off.
In this circuit, however, a very high frequency clock frequency and other related fast logic circuits are needed to achieve sufficient DPWM resolution at high switching frequency. Therefore, the power consumption is very high. In addition, in multiphase applications, this circuit cannot be easily shared among phases, so independent counter-comparator pair is needed for each phase. This increases the die area and power consumption even further.
The second technique is using dither methods. By using dither methods, the least significant bit (LSB) of the duty cycle is alternating between 0 and 1 in a specific pattern during the steady state operation. As a result, the effective resolution of DPWM is increased.
FIG. 1B shows a dither generation scheme based on a look-up table 116. In the proposed look-up table 116, 2M dither sequences are stored for the M LSBs of the duty cycle value. Each sequence is M bit long. By selecting the dither sequence corresponding to the appropriate M LSB's value, M bit counter sweeps through this dither sequence. By using this dither pattern, the effective DPWM resolution is increased by M bits.
By using dither methods, however, sub-harmonics may occur, with frequency lower than the switching frequency. This may cause electromagnetic interference (EMI) problems during the operation and an audible noise from magnetic components.
Tapped delay line techniques have also been used to achieve high resolution DPWM. The essential components of the tapped delay line DPWM circuit are the delay line 120 and multiplexer 124, as shown in FIG. 1C.
A pulse from a reference clock 128 starts a cycle and sets the DPWM output to go high. The reference pulse propagates through the delay line 120, and when it reaches the output selected by the multiplexer 124, the DPWM output 132 goes low. The total delay of the delay line 120 is adjusted to match the reference clock period.
A disadvantage of this method, however, is that the size of the multiplexer 124 increases exponentially with the number of resolution bits. Another drawback is that when this technique is applied to multiphase applications, precise delay matching among the phases places a stringent symmetry requirement on the delay line 120. Also, the delay line 120 is an analog circuit element and is not area efficient for high resolutions.
Another solution is using a ring oscillator 136, as shown in FIG. 1D. The above configuration is composed of 128 stage differential ring oscillators, which yield 256 symmetrically oriented taps, and a 256-4 multiplexer (MUX) 140 that can select the appropriate signals from the ring. During the operation, a square wave propagates along the ring. When the rising edge reaches tap zero in the ring, the rising edge of the PWM signal for phase one is generated. The falling edge of this PWM signal is generated when the rising edge of the propagating square wave reaches a specified tap in the ring. This scheme has the advantage of symmetric structure and is therefore suitable for multiphase applications. This scheme, however, has similar area inefficiencies as the delay line.
Therefore, there remains a need to overcome the inherent problems associated with analog components of a power supply as well as the inherent problems associated with digital control power supplies.